Power dissipation is a significant problem in conventional integrated circuits. In many applications, the performance of integrated circuit devices is limited by the amount of energy consumed by the circuitry implementing a function rather than by the die area of the circuitry. A large fraction of the power dissipated in conventional digital integrated circuits is consumed in the clock network. The amount of energy that is consumed by flip-flops due to data transitions is small because the activity factor, the fraction of time the data input of the flip-flop toggles, is quite low, typically about 5-10%. In contrast, the clock input load and clock energy is a particularly important metric for determining the energy that is consumed by the latches and flip-flops. Hence reducing the clock-switched capacitance by a given amount may produce a greater power savings compared with reducing the data-switched capacitance by the same amount.
Accordingly, what is needed in the art is a latch circuit that reduces the clock energy by reducing the capacitance of clock loads. Thus, there is a need for addressing these issues and/or other issues associated with the prior art.